Abstract
The present disclosure is directed to eliminating adverse capture timing modes in static timing analysis (STA) through design. In high-performance integrated circuits, such as system-on-chip (SoC) designs, functional paths across independent intellectual property (IP) blocks are traditionally tested for stuck-at faults using a common slow-frequency off-chip clock. This may create complex timing closure scenarios due to large clock skew and crosstalk across IP boundaries. Large High Performance Compute SOCs in small technologies and specifically AI/ML Chips with high number of Multi Instantiated modules possess large volume of such paths.The present disclosure utilizes on-chip clock controllers (OCCs) within each IP block to generate capture pulses in a staggered fashion. By programming the OCCs to offset capture pulses by multiple clock cycles, synchronous paths between IP blocks are prevented from failing hold timing. This staggered clocking approach eliminates the need for dedicated slow capture STA signoff modes and physical implementation constraints, significantly reducing compute resources and engineering time required for timing closure while maintaining high stuck-at fault coverage. Key words include Static Timing Analysis(STA), High Performance compute (HPC), Design for Test (DFT) , DFT STA, System on Chip (SOC), Hold Timing, Setup Timing, On chip clock controller (OCC).
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "ELIMINATING STUCK AT CAPTURE MODE IN STATIC TIMING ANALYSIS BY DESIGN", Technical Disclosure Commons, (March 19, 2026)
https://www.tdcommons.org/dpubs_series/9563