Abstract
Manufacturing costs for System-on-Chip (SoC) devices increase as silicon process nodes advance. Using a single high-end SoC for both premium and entry-level product tiers often results in unused features and reduced margins for lower-tier devices. Conversely, designing separate SoCs for each tier may require multiple expensive tape-outs. This disclosure describes a method for creating multiple product variants from a single base silicon wafer using metal layer customization. A monolithic SoC die is designed with all necessary functional blocks, including processing cores, memory controllers, and interfaces. Two such dies are placed adjacently on a wafer. In a first configuration, metal layers are used to selectively interconnect the adjacent dies, doubling processing resources and memory bandwidth to form a premium tier device. In a second configuration, the metal traces are omitted, allowing the dies to function as independent, lower-tier SoCs. This approach enables scalable performance and functional differentiation while improving design and manufacturing overhead.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Masterson, Tony and Dasari, Uday Kumar, "Scalable System-On-Chip Architecture via Selective Interconnection of Adjacent Die Blocks", Technical Disclosure Commons, (March 05, 2026)
https://www.tdcommons.org/dpubs_series/9456