Abstract
In VLSI physical design, a Hard Macro (HM) instantiation with a vertical and horizontal cut can often intrude into the logic placement area. Typically, all routing layers are blocked in HMs. As a result, any nets passing through the area face a routing resource crunch that can cause routing congestion and design rule check (DRC) failures. This disclosure describes techniques for creating an HM instantiation during the PD phase of a digital design with a diagonal cut. The HM instantiation is cut using small notches formed by short vertical and horizontal cuts, which cumulatively provide a cut that is effectively similar to a straight diagonal cut. The designer can leverage the diagonal cut to avoid the inefficiencies in the design floorplan that result from the intrusion of HM partition corners into the logic placement region. Employing a diagonal cut can nearly eliminate shorts violation counts and DRC failures compared to the standard HM instantiations. This helps designers distribute routing and placement resources more uniformly across the design with a corresponding positive impact on the rest of the PPA metrics. The use of a diagonal cut can resolve routing congestion in the design of any VLSI chip.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Waghmare, Sachin Ramrao, "Physical Design with Diagonal Cut Floorplan to Resolve Routing Congestion Hotspots", Technical Disclosure Commons, (February 11, 2026)
https://www.tdcommons.org/dpubs_series/9320