Abstract
Traditional JTAG data transfers often face limitations due to the “stop-and-wait” nature of the IEEE 1149.1 protocol. High overhead is introduced because the Test Access Port (TAP) state machine must be transitioned between SHIFT-DR and UPDATE-DR states for every individual data word. This disclosure describes a JTAG-to-AXI bridge microarchitecture that implements a streaming-write mechanism. A Command FIFO is utilized to decouple JTAG programming from AXI bus execution. An internal bit-shift counter and control logic are employed to automatically push data into a Write FIFO after a fixed number of bits are shifted. This allows a JTAG host to remain in a single SHIFT-DR state while continuously streaming large data blocks. Throughput is significantly increased by eliminating the clock cycle overhead associated with repeated state machine transitions during bulk data transfers to AXI subordinate peripherals.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Ellur, Harsharaj, "Continuous Data Streaming via a JTAG Interface", Technical Disclosure Commons, (February 11, 2026)
https://www.tdcommons.org/dpubs_series/9317