Abstract
Testing calibrated delay circuit (CDC) propagation delay at high double data rate (DDR) speeds is often limited by inaccuracies and increased test time in automated test equipment (ATE). Traditional characterization methods may be impacted by external hardware parasitics that degrade accuracy, as well as specialized tools that may increase both test time and overall cost.
This disclosure describes an on-chip analog design-for-test (DFT) method that utilizes a phase frequency detector (PFD) from an existing phase-locked loop (PLL) to measure CDC delay. The calibrated clock and reference clock are routed to the PFD to convert the delay into a duty cycle. This time-domain signal is processed through an resistive-capacitive (RC) circuit to generate a voltage equivalent, which is then digitized by an analog-to-digital converter (ADC) for comparison against calibration registers. This approach improves measurement accuracy and reduces test costs by performing characterization directly on-chip with minimal design changes.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Subramanian, Karthikeyan; Chunduri, Kasi; Goyal, Mukesh; Vethanayagam, Dhivyabharathi; Gurumoorthy; and Gupta, Durgesh, "Testing Calibrated Delay Circuit Propagation Delay with a Phase Frequency Detector", Technical Disclosure Commons, (February 02, 2026)
https://www.tdcommons.org/dpubs_series/9261