Abstract
During semiconductor design-for-test operations, the application of high-activity test patterns can generate localized heat as functional-mode thermal management systems may be inactive. A hardware-based architecture can integrate localized monitoring modules near potential thermal hotspots. A module can operate synchronously with test patterns to capture peak temperature values and their corresponding test pattern counts. The system may also include a mitigation circuit that compares real-time temperature against a configurable threshold and can throttle system clocks if the threshold is exceeded to reduce heat generation. This approach can provide thermal observability and control in a test environment, enabling the creation of thermal profiles for test program optimization and providing a mechanism to mitigate thermal runaway.
Publication Date
2026-01-07
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Vasa, Veerabhadra Rao; Jalasutram, Maheedhar; Kota, Aditya; and G, Swathi, "On-Chip Thermal Monitoring and Mitigation for Semiconductor Design-for-Test", Technical Disclosure Commons, (January 08, 2026)
https://www.tdcommons.org/dpubs_series/9147