Abstract
The present disclosure is directed to a quad-phase smart power stage (SPS) designed to address the increasing power demands of high-performance computing and machine learning processors such as hardware accelerators, tensor processing units (TPU), graphics processing units (GPUs), and high-performance system on chips (SoCs) in densified data centers. Existing dual-phase power solutions may not meet the rising current density requirements and are limited by a larger physical profile. The present disclosure integrates four power stages into a single, compact package (e.g., 7x7 mm), enabling the creation of a densified vertical power (VPWR) building block. This high-integration architecture can achieve a significantly higher current density (e.g., 2.5–3.1 A/mm²) compared to traditional solutions. Furthermore, the present disclosure allows for a lower module profile (e.g., 5 mm height) and facilitates uniform current distribution, which can reduce power delivery network (PDN) losses. The combination of higher current density, lower profile, and improved efficiency can provide an efficient power delivery solution for next-generation computing and machine learning hardware.
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Recommended Citation
N/A, "NEW QUAD-PHASE SMART POWER STAGE FOR HIGHER CURRENT DENSITY VERTICAL POWER MODULE", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/9054