Abstract
This disclosure describes techniques of design-aware test-point (DATP) insertion for the automatic test pattern generation (ATPG) testing of digital circuits characterized by relatively large, protocol-based register arrays with multiple, non-overlapping address spaces that use a single output data bus. The problem of common address space across register banks in such circuits is solved by introducing test points that effectively parallelize address-space access. Test points are introduced to enable local generation of byte-select, read, write, and bank-select signals, and to observe and control decoding logic. The presence of these test points enables the ATPG tool to produce a compact test-vector set that achieves a high fault coverage per pattern at a low test cycles per fault (TCPF). Two-level-one-hot, independent control of each read-data bus and of the common bus further reduces the effort of the ATPG tool and enables it to generate a dense test-vector set. The described test points incur a low area overhead.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Vasa, Veerabhadra Rao and Gottumukkala, Rajesh, "Design-aware Test-Point Insertion for Efficient Automatic Test Pattern Generation", Technical Disclosure Commons, (November 07, 2025)
https://www.tdcommons.org/dpubs_series/8846