Abstract
This disclosure describes a method and system for mitigating aging effects in on-chip clock-gated trees within integrated circuits, particularly in high-frequency designs like those found in server and mobile processors. The technique involves strategically controlling the propagation of logic 0 or 1 signals through clock-gating circuitry using a multiplexer, which is managed by a hardware state machine or software. This controlled propagation aims to balance the asymmetric aging of transistors that typically occurs when clock nodes are stuck at a particular value for extended periods. By periodically alternating the propagated logic state, the approach ensures that both parts of the clock tree experience aging in inverse directions, thereby nullifying or significantly reducing the overall degradation effect on clock waveform integrity and duty cycle over time.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Method to Reduce Aging Effects in On-Chip Clock Gated Trees", Technical Disclosure Commons, (October 16, 2025)
https://www.tdcommons.org/dpubs_series/8733