Abstract
Complex application-specific integrated circuits (ASIC) often include uncontrollable or unobservable logic, posing a significant testing challenge. This disclosure describes test-point insertion (TPI) techniques that reduce the number of test-point components in ASICs by reusing existing functional sequential elements, thereby reducing leakage current, power consumption, and design area. Per the techniques, functional flip-flops which can potentially be used as control or observe test-points are identified. An additional exclusive-or (XOR) gate is added on existing functional paths to get observability. The control and observe test-point nodes are separated and categorized as ‘control test point list’ and ‘observe test point list’. To effect area- and power-efficient TPI, for each node in each list, a target register is identified; its clock domain is determined; a proximal, clock-domain-aligned candidate scan flip-flop is identified; conflicts checked for; and the output of the scan flip-flop or of the XOR gate is connected to the control logic circuitry.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Siddhapathak, Krunal; Patel, Divya; Gonugunta, Vevekanenda; and Garg, Ankit, "Test Point Insertion in VLSI to Optimize Area and Power Consumption", Technical Disclosure Commons, (August 08, 2025)
https://www.tdcommons.org/dpubs_series/8441