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Abstract

A translation lookaside buffer (TLB) is a fast cache that stores recent page table entries to enable efficient translation between virtual and physical memory addresses. TLB entries include architected hint bits that can be used to provide information about the nature of the memory access. Current TLB implementations associate hint bits with physical pages, limiting their flexibility. This disclosure describes techniques to dynamically control hint bits by embedding them directly within the virtual address. New instructions can be introduced that either directly specify the hint bits or provide a register holding them. The provision of such new instructions enables hints to be incorporated into the accessed virtual address during address generation. Alternatively, the virtual address can be edited directly prior to use by a conventional load or store instruction. The techniques advantageously enable dynamic hint control, promote code simplicity, enable context-aware use of hint bits, and improve cache utilization, memory latency, and performance.

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Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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