Abstract
To fetch and execute instructions ahead of time, processors try to predict the outcome of conditional branch instructions before they actually execute. A correct prediction allows a pre-computed result to be used instead of waiting to execute the instruction, thereby speeding up program execution. With indirect branches, the target is unknown until runtime, making prediction much harder. This disclosure describes techniques to improve the outcome of processor speculation by extending the instruction set architecture (ISA) to include a hint instruction that indicates the most likely address of the next indirect jump. The hardware may use the information provided in the hint instruction to improve speculation and to reduce indirect branch mispredictions. This can improve performance by increasing the likelihood the correct branch is taken and the correct instruction sequence is speculatively executed.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
NA, "Extending Instruction Set Architecture to Include Indirect Branch Hints", Technical Disclosure Commons, (June 17, 2025)
https://www.tdcommons.org/dpubs_series/8238