Abstract
The lifespan of NAND-based flash memories is limited by physical properties of flash cells. The reliability of retrieving data stored in flash memories can deteriorate over time. This disclosure describes techniques to manage flash-memory reliability by monitoring bit error rate (BER) per physical memory block and by taking certain actions based on the observed BER. Such actions include ignoring BERs that are low enough to be recovered by an error-correcting code (ECC) without impacting performance or reliability and notifying the processor if the BER rises to high levels. Ignoring low BERs, e.g., not escalating low BER rates to the processor, maintains high compute performance. Escalating higher BERs to the processor enables the firmware to take actions appropriate to the measured BER. For example, the action for high BERs may include putting the corrupted block on a pending re-scan list to monitor BER trends for the block, while for still higher BERs, the action may be moving the data to a different location.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
NA, "Managing Flash-Memory Reliability by Proactive Monitoring of Bit Error Rate", Technical Disclosure Commons, (June 04, 2025)
https://www.tdcommons.org/dpubs_series/8190