Abstract
Modern low-power system-on-chip (SoC) designs reduce power consumption by using multiple asynchronous clocks that can run different chip blocks at their optimal DVFS (dynamic voltage frequency scaling) points. However, this causes significant increases in instances of data paths crossing asynchronous clock domains. At such crossover points, synchronizer is used in the design to address metastability issues. Typically, the synchronizer cells comprise two or three stages of flip-flops, but such synchronizer cells are implemented as single-bit standard cells. As a result, the design is restricted from achieving a higher multi-bit grouping ratio and a better performance-per-Watt. This disclosure describes a multibit synchronizer that can address the issue of low multibit conversion ratios in designs with numerous asynchronous clock-domain crossings. The described multibit synchronizer cell can improve the multi-bit grouping ratio, resulting in higher multi-bit conversion ratios and average number of bits per synchronizer, ultimately leading to reduced power consumption.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
De, Kanishka and Lin, Sheng, "Multibit Synchronizer for Ultra-low-power Multi-clock System-on-Chip", Technical Disclosure Commons, (May 19, 2025)
https://www.tdcommons.org/dpubs_series/8138