Abstract
The technology described in this paper relates to an artificial intelligence (AI) accelerator chip's application-specific integrated circuits (ASICs)’ power down for idle power reduction, and low-latency peripheral component interconnect express (PCIe) relink made on AI accelerator chips. Complete turning on or off of the AI accelerator chips may be accomplished by leveraging various software and/or hardware components in the AI accelerator systems. The specialized software and/or hardware may be configured to turn off the entirety or only certain components of each AI accelerator chip, such as application-specific integrated circuits (ASICs) embedded in the AI accelerator chip, and remove individual PCIe links between the host system and the AI accelerator chips.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "SAVING IDLE POWER AND ENGINEERING HOURS BY POWERING OFF/ON IDLE AI ACCELERATORS", Technical Disclosure Commons, (May 09, 2025)
https://www.tdcommons.org/dpubs_series/8103