Abstract
Performing quality control on any system-on-a-chip (SoC) requires testing wafers and packages at multiple sites to save testing time and costs. Currently, the parallelism feasible with multisite testing is limited by the number of Input/Outputs (IOs) required because typical testers provide only a limited number of IO channels. This disclosure describes a circuit architecture to reduce the number of scan IN and scan OUT pins for multisite SoC testing by providing scan INs and scan OUTS from the same input port. The scan OUT comparison can then be performed internally within the SoC via one status bit. The status bit can be implemented as dedicated IO, or can be captured in a register that is read via the Joint Test Action Group (JTAG) interface on Test Data Output (TDO). The techniques can be implemented to support any type of multisite testing within any SoC. Implementation of the techniques can help achieve higher parallelism in multisite testing. The increase in parallelism can yield substantial time and cost savings, providing higher throughput and lower time to market.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Grover, Achin; Mittal, Deepak; Chittora, Atul; and Parasrampuria, Mayank, "Architecture to Increase Parallelism in Multisite Testing by Reducing I/O Scan Pins", Technical Disclosure Commons, (May 06, 2025)
https://www.tdcommons.org/dpubs_series/8091