Abstract
This disclosure describes techniques to detect panel cracks in organic light emitting diode (OLED) based display modules. A stress test is performed to identify weak or defective components that may fail prematurely during regular use of the display modules. The stress test includes testing the display panel from a display driver integrated circuit (DDIC) output trace all the way to the panel internal trace. The display panel traces are toggled at a high toggling rate between a ground voltage and an elevated analog supply voltage (AVDD). In some implementations, the AVDD may be set to a level greater than the regular operating voltage. The toggle frequency can be the fastest speed achievable by the DDIC. Applying the high voltage pattern at a high toggling rate can trigger defects in defective display modules. Following the stress test, the display panel is inspected for display panel line defects.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Wei-Hsiang, Hung and Choi, Sangmoo, "Early Detection of Panel Cracks in Display Modules", Technical Disclosure Commons, (December 11, 2024)
https://www.tdcommons.org/dpubs_series/7643