Abstract
This disclosure describes techniques that enable the use of faulty semiconductor chips to achieve reliable large language model (LLM) performance. The output of a faulty chip is subjected to a chip-specific transformation that corrects errors. Error-correcting transformations are applied at a relatively large scale, e.g., for an entire LLM layer rather than at the level of a single matrix multiplication block. The use of unreliable components to achieve reliable computing reduces the rejection rate, and correspondingly increases the yield of semiconductor manufacturing. With the scale at which error correction is applied, costly die-size and energy consumption redundancies are reduced or eliminated.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Lupi, Roberto, "Semiconductor Yield Improvement by Enabling Use of Faulty Chips for LLM Inference", Technical Disclosure Commons, (November 15, 2024)
https://www.tdcommons.org/dpubs_series/7534