Abstract
This disclosure describes techniques to provide high bandwidth connectivity for chip packages. Per techniques of this disclosure, a two-tiered chip package is provided that includes two tiers of substrates. A first tier (Tier 1) substrate includes an application-specific integrated circuit (ASIC) substrate that is utilized to house the chips while a second tier (Tier 2) substrate includes a substrate like PCB (SLP) substrate or a high density interconnect (HDI) that is utilized to provide connectivity via a CPC connector. Micro ball grid arrays (BGAs) are provided on the tier 1 substrate, while BGA balls with a pitch greater than 1 mm are mounted on the tier 2 substrate. The two-tiered package is soldered down on the main board. An elastomer connector is then placed and a mechanical load is applied to enable connection of the CPC connectors.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Two-tier Chip Packaging for High-Bandwidth Communication", Technical Disclosure Commons, (August 01, 2024)
https://www.tdcommons.org/dpubs_series/7254