Abstract
Chip-to-chip (CTC) connections often involve serializing parallel data. This serialized data is transmitted at a higher frequency than parallel data and is usually subject to a high bit error rate, compared to the error rate associated with normal flop-to-flop data movement within a single die. Error-Correcting Code (ECC) and Forward Error Correction (FEC) are often used as a detection and correction methods. However, each has limitations and neither error correction method allows for correction of a 100% bad link, due to a manufacturing defect (stuck at) or other defect. Techniques presented herein provide for interleaving multiple ECC payload and checksums across lanes of a 2.5D parallel CTC application, which allows for correction of any number of errors on a bad link, up to correcting all of the data on a completely bad link. Techniques presented herein may allow for a more robust communication channel that can potentially increase the yield of Application-Specific Integrated Circuit (ASIC) manufacturing processes, thus reducing cost.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Lawson, Todd, "ENHANCED ERROR DETECTION AND CORRECTION IN HIGH SPEED CHIP TO CHIP CONNECTIONS", Technical Disclosure Commons, (January 17, 2021)
https://www.tdcommons.org/dpubs_series/3974