Abstract
In certain ASICs, the input-output (I/O) interfaces, such as high-bandwidth memory (HBM) physical layer (PHY), serdes, etc., occupy substantial area on the die. Validation of I/O interfaces fabricated in recent process nodes, e.g., 3 nm technology, is generally more involved and has corresponding time to market costs. For high-performance ASICs whose compute function is divided amongst cores, communications between an HBM and the core farthest from it can be complex. This disclosure describes techniques to partition the compute cores and the I/O interface into separate dies and to implement these in suitable process nodes which may be different, e.g., compute core in 3 nm technology and I/O interface in 7 nm technology. By doing so, the time to validate the I/O interface is reduced. Additionally, communication lines between an HBM and a compute core far away from each other are simplified. Another benefit is that the area of compute core dies can be maximized due to no other I/Os.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "Three-dimensional Integration of Compute Core and I/O in High-performance ASIC", Technical Disclosure Commons, (October 05, 2020)
https://www.tdcommons.org/dpubs_series/3655