Abstract
Serial peripheral interface (SPI) is a protocol that enables low-level machine communication between electronics subsystems, e.g., microcontrollers, peripherals, etc. In applying SPI to communications between devices of substantially differing performance characteristics, e.g., clock frequency, memory capacity, or response time, the original SPI has some disadvantages. For example, due to the streaming nature of SPI communication, errors are not detected; due to differing clock frequencies at two ends, synchronization is difficult; due to differing memory capacity at two ends, the buffers of the end with less memory overflow; etc.
This disclosure describes an extension to SPI that features synchronization signaling and packet-splitting abilities to enable devices of differing abilities to communicate via SPI. The extension also enables asynchronous transaction execution over the SPI bus and adds error detection capabilities, both features that enable larger packet sizes and higher transmission/transaction rates.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Lobachev, Leonid, "Extended SPI Bus", Technical Disclosure Commons, (August 09, 2018)
https://www.tdcommons.org/dpubs_series/1394