Abstract
A hardwired application-specific integrated circuit (ASIC) or a statically configured field-programmable gate array (FPGA) in an always-on co-processor carries logic fixed at design time, which can allow environment-specific noise to trigger repeated false wakes of a host processor. To reduce false-wake overhead and support runtime adaptation, this disclosure describes a self-adapting co-processor system built on a coarse-grained reconfigurable array (CGRA) or a synchronous look-up table (LUT) overlay. The system evaluates each sequence-tagged ingress frame on a committed plane and on a candidate plane and scores both against a delayed ground-truth label. A surprise ring buffer captures false wakes and disagreements, and a netlist synthesizer compiles a candidate synchronous netlist from those episodes during a maintenance state. Once the candidate plane outscores the committed plane by a hysteresis threshold, the system promotes the candidate plane. This approach can reduce false-wake battery drain without interrupting live execution.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Murphy, Jonathon, "Self-Adapting Reconfigurable Co-Processor with Hardware Shadow Verification and Episodic Replay", Technical Disclosure Commons, (November 09, 2026)
https://www.tdcommons.org/dpubs_series/12832