Abstract

Silence Is Not Absence: Three-Valued Verification of Command-to-Effect Correspondence Across CPU Memory, DMA, Devices and Networks

Abstract:

A device raises a completion interrupt. A NIC counter increments. A telemetry dashboard shows no errors. Each of these is routinely taken as proof that a command actually reached its target and produced the intended effect. None of them proves it. The buffer may have been reused, the device reset, the firmware replaced, the IOMMU mapping reassigned, the request rewritten by a proxy, or the telemetry simply not looking at the right moment. As AI agents and automated operations systems increasingly act on these signals, retrying, remediating or reporting success, misreading hardware evidence becomes a direct cause of duplicated, lost or misdirected actions.

This disclosure describes a vendor-neutral method for deciding what hardware and system evidence actually proves about the link between a source operation and a later effect. The six events involved are command preparation in processor memory, DMA buffer ownership, descriptor queue occupancy, device consumption, local completion and external effect, and the method treats each as a separate fact. Three ingredients drive the reconstruction. Generation-qualified identity attaches a generation or epoch value to every buffer, descriptor slot, device function, firmware image and address mapping, so reuse and reset are detected instead of being mistaken for continuity. Measurement coverage records what each observation could and could not see, so missing telemetry is never read as a negative result. Source dependency tracks which signals derive from the same origin, so correlated signals are not counted as independent confirmation.

Mandatory predicates covering memory state, DMA ownership, descriptor occupancy, firmware epochs, device consumption, hardware telemetry, packet correspondence and proxy or gateway request transformation are combined with strong-Kleene-style three-valued logic. The output is CONSISTENT when complete supporting evidence exists, INCONSISTENT when a contradiction is proven, and UNRESOLVED when evidence is missing. Verdicts are observational conclusions only, never execution authority and never a guarantee of delivery.

The disclosure provides a seven-phase, forty-two-stage workflow, twelve distinguishing technical steps, six embodiments, formal predicates, failure cases and forty implementation checkpoints. A reproducible synthetic laboratory in Python, Go and JavaScript runs 48 shared fixtures across 154 test executions, all passing. End-to-end latency is modelled analytically at 1.40 ms in an illustrative budget; measured timings of about 1.0 to 4.5 microseconds per call cover only in-memory evaluators. All results are self-authored, not peer reviewed, and not independently or field validated.

This disclosure is based on the Mothership application PCT/IB2026/055615, filed 4 June 2026 and publicly disclosed 16 July 2026, which claims priority from PCT/IB2026/053385, filed April 2026 and publicly disclosed 4 June 2026. The author is open to strategic collaboration, licensing or acquihire discussions.

Keywords: completion interrupt; command-to-effect verification; DMA buffer ownership; IOMMU and SMMU mapping; descriptor ring; device queue consumption; device reset; firmware epoch; generation counter; ABA problem; telemetry coverage; observability blind spots; silent failure; silent data corruption; packet correspondence; proxy request rewriting; source dependency graph; three-valued logic; strong Kleene logic; AI agent safety; AIOps; DPU; SmartNIC; GPUDirect.

Suggested CPC classes (for search): G06F 11/30; G06F 11/3466; G06F 11/0751; G06F 13/28; G06F 12/1081; G06F 21/57; H04L 43/08; G06N 5/04.


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Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial 4.0 License

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