Abstract

Execution-Finality Enforcement Profiles for the Core Finality Mechanics and for AI Accelerators, CXL and UCIe Fabrics, IOMMU, HBM, DPUs, Co-Packaged Optics, Roots of Trust and Package Interconnect

Most authorisation lives in software, but AI infrastructure increasingly acts below it: accelerator outputs leave over scale-up fabrics, CXL memory is pooled and reassigned, chiplets join over die-to-die links, DMA and pre-translated requests bypass software checks, DPUs move data without the host, and optical lanes, firmware, link, power and test states change what hardware can do. Attestation, IOMMU configuration and secure boot establish trusted environments and coarse limits; none binds a specific operation, at the moment it is accepted, to current authority. This disclosure presents 48 enforcement profiles and the core finality mechanics on one architecture: each operation is held as a non-effective candidate act; a protected enforcement domain commits validation evidence and issues single-use, non-bearer authority bound to the exact act, current state and enforcement point; and a gate at the first usable effect reconstructs the actual pending operation and verifies it before release, failing closed otherwise. Key concepts disclosed include: computation is not authority to release, so an output can be computed but not leave; evidence must be committed before authority becomes usable; the gate rebuilds the real pending operation instead of trusting the caller's description; verification and consumption happen atomically with the hardware commit; two independent protected domains cross-commit collection-time and execution-time evidence; old epochs and generations always fail; and every alternate path to the same effect, including DMA, debug, test and failover paths, must pass an equivalent gate. Silicon profiles cover CXL extents, UCIe chiplets, HBM ownership and residual state, IOMMU, PASID and ATS, confidential accelerator secrets, DPU host-bypass denial, co-packaged optics, root-of-trust and firmware activation, IDE/TDISP state, inference-output release and model-weight activation. Alignment is discussed with publicly described directions at NVIDIA, AMD, Intel, Arm, Qualcomm, Huawei, Broadcom, Marvell, Google, Microsoft and AWS, including rack-scale accelerator systems, scale-up interconnects and confidential computing. This alignment material is AI-generated; readers must cross-check it against the original patent filings before drawing conclusions. This disclosure is based on PCT/IB2026/055615 (the "Mothership" application), filed 4 June 2026 and disclosed 16 July 2026, which claims priority from PCT/IB2026/053385, filed 7 April 2026 and disclosed 4 June 2026, and on PCT/IB2026/054453, filed 5 May 2026 and disclosed 16 July 2026. The author is open to acquihire or strategic collaboration.

KEY INVENTIVE CONCEPTS 1. Computation is not release authority: a computed output stays non-effective until separately authorised to leave the hardware. 2. Evidence before authority: protected validation evidence is committed before, or atomically with, any usable permission. 3. Non-bearer, act-bound authority: permission is tied to the exact operation, current state, epoch and one enforcement point, and is single-use. 4. Boundary-local reconstruction: the gate rebuilds the actual pending operation itself rather than trusting a supplied digest. 5. Atomic verify-and-commit in hardware: checking, consuming authority and committing the effect happen as one step. 6. Two-instance cross-commitment: independent protected domains bind collection-time and execution-time evidence, and neither alone is authority. 7. Fencing by generation: authority from an older lease, ownership or revocation epoch always fails. 8. Path completeness: DMA, peer-to-peer, debug, test, loopback, error and failover paths must cross an equivalent gate or be disabled. 9. Hardware sinks below the software stack: gates sit in memory controllers, fabric routers, IOMMUs, DPUs, optical lane controllers and package interconnects.

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