Abstract

Execution Finality for AI-Factory Silicon: 98 Enforcement Profiles for GPUs, Chiplets, Memory Fabrics, CXL, RDMA, DPUs, Photonics and Package Interconnect

In an AI factory, the part that computes a result is rarely the part that makes it real. A GPU calculates a tensor, but a DMA or RDMA engine moves it; a scheduler picks a placement, but a partition controller commits it; a model selects an output, but a NIC, optical lane or token gate releases it; a controller decides a cooling change, but a pump actuates it. Authentication, access control, workload identity, attestation, confidential computing, IOMMU and SMMU isolation, encryption, signed firmware and hardware roots of trust are all necessary, yet none of them alone decides whether the exact pending transfer, memory mapping, route, firmware activation, optical enable or actuation is still authorised at the instant and location where it takes effect — and many of these effects happen at line or memory-transaction rate, too fast for a remote authorisation round trip. This paper presents 98 enforcement profiles that place a verify-and-commit gate at the component that physically controls each consequence: accelerator egress controllers, HBM and memory controllers, KV-cache page leases, model and adapter loaders, mixture-of-experts dispatch registers, GPU partitions, NVLink-class and Ethernet or InfiniBand fabrics, SuperNIC and RDMA memory keys, DPUs, CXL memory pools and coherence logic, UCIe chiplet sideband, die-to-die links, JTAG and debug ports, package firmware, eFPGA bitstreams, silicon-photonic lanes, modulators and lasers, rack power and liquid cooling, and PCIe/CXL link-layer credits, link training, retimers, posted writes, IDE/TDISP state, power rails, error paths and test modes. Each operation is held pending; its exact parameters are bound to a narrow, single-use permit tied to current state, epoch, freshness and the specific gate; and the gate commits only if all still match, failing closed otherwise. The paper gives the common invariants, reference check-and-commit pseudocode, cross-domain examples, implementation variations and alignment with publicly described directions at NVIDIA, AMD, Intel, Arm, Broadcom, Marvell, Google, Microsoft, AWS, Meta and telecom vendors. The industry-relevance and alignment material was generated with AI assistance; readers must cross-check it against the original patent filings and each company's own public documentation before drawing any conclusion. This disclosure is based on the author's international patent application PCT/IB2026/055615 (the "Mothership" application), filed on 4 June 2026 and publicly disclosed on 16 July 2026, which claims priority from PCT/IB2026/053385 (the ALF application), filed on 7 April 2026 and publicly disclosed on 4 June 2026. The author is open to acquihire or strategic collaboration. IETF Datatracker: https://datatracker.ietf.org/doc/draft-das-ai-factory-silicon-finality/

KEYWORDS AI factory, AI infrastructure security, GPU security, AI accelerator, HBM, KV cache, mixture of experts, NVLink, InfiniBand, RoCE, RDMA, SuperNIC, DPU, SmartNIC, CXL, cache coherence, UCIe, chiplets, JTAG, firmware security, eFPGA, silicon photonics, co-packaged optics, liquid cooling, PCIe, IDE, TDISP, IOMMU, SMMU, confidential computing, hardware root of trust, zero trust, execution finality

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