Abstract
A data transfer between memory interfaces of unequal bus width and latency loses much of the available bandwidth when a central processing unit (CPU) drives the transfer with ordinary load and store instructions. A secure subsystem often has no hardware direct memory access (DMA) engine. To address these deficiencies, this disclosure describes a software-emulated direct memory access (SW-DMA) method that maps a destination region as write-back cacheable memory and coalesces narrow stores in a level one (L1) data cache into complete lines. A cache clean instruction then hands each completed line to a hardware cache controller for a full-width burst. A sliding window loop overlaps the burst for one block with the loads for a later block, so the SW-DMA method can raise throughput several times over without a dedicated DMA engine.
Creative Commons License
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Recommended Citation
Yadav, Mohit, "Software-Emulated Direct Memory Access Across Asymmetric Memory Interfaces Using Cache Line Coalescing and Asynchronous Cache Controller Write-Back", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/12715