Abstract
A conventional hard peak current controller for a system on a chip (SoC) restricts the operating frequency of the SoC whenever the instantaneous current crosses a hard peak current limit. The resulting reactive throttling methodology can degrade SoC performance during transient, high-demand workloads. To address this limitation, this disclosure describes a hierarchical peak current management system that augments the hard peak current controller with a multi-time-scale current monitor, a peak monitor, and a peak current predictor. Each of these elements produces an operating point cap for the corresponding intellectual property (IP) blocks based on sustained demand, proximity to the hard peak current limit, or predicted future demand. An arbitrator combines the caps into final operating points. The system can reduce engagement of the hard peak current controller while keeping that controller as the final protection against severe current excursions.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Heidarinejad, Mohsen; Kenarangi, Farid; and Mittal, Arpit, "Hierarchical Peak Current Management for Systems on a Chip Using Multi-Time-Scale Current Observation, Peak Proximity Detection, and Prediction", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/12214