Abstract
One radio module, about 22 x 34 mm, with a single row of 16 host castellations on one short edge and 7 castellations on the opposite edge (mostly ground, two carrying the SWD debug port). It contains the radio chip (an EFR32FG23 sub-GHz SoC in the product, or an Si4463 transceiver in the prototype), its RF front end and PA, a metal shield can, its own antenna connector (u.FL), its own regulator fed from the host’s 3.3 V, buffers on every host line, and an ID EEPROM. RF never crosses the host edge. The module is either reflowed flat onto the pack’s board, or reflowed flat onto a passive M.2 2242 key-B carrier card that plugs into an M.2 key-B socket on the rack’s mainboard. The carrier’s finger map is safe against cross-insertion in both directions: +3.3 V only on the five M.2-standard 3.3 V fingers, ground on the standard ground and CONFIG fingers, signals only on fingers where a standard card or host meets at worst another logic signal, and every other finger unconnected. Castellation 9, nBOOT (active low, pulled up and buffered on the module), lets any host force the radio’s bootloader by holding it low while SDN releases the radio from reset; one host line can serve several modules. SWCLK and SWDIO are on ground-edge castellations 19 and 20, with 100 ohm series resistors at the chip.
Creative Commons License
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Recommended Citation
Anonymous, "One castellated radio module mounted either flat on a body-worn receiver or on a cross-insertion-safe M.2 key-B carrier, with debug on ground-edge castellations, a forced-bootloader line and first flash by the host CPU", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/12142