Abstract
A clock manager for a sequential digital block samples a single activity indicator signal and applies a single hysteresis duration before it stops the clock of the sequential digital block. Because that duration is sized for the worst-case activity category, a rare or infrequent activity can hold the clock running longer than the activity warrants. To address these deficiencies, this disclosure describes a graded hysteresis counter system that accepts a plurality of wakeup conditions, each paired with a programmable hysteresis register. A count floor logic selects the largest hysteresis value among the active wakeup conditions as a count floor. A running down-counter loads that count floor where the running count is lower, decrements the running count where it is higher, and reports expiry where the running count reaches zero. In this way, each category of activity can receive a hysteresis duration matched to the frequency and urgency of that category, and clock gating residency can improve.
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Recommended Citation
Majumder, Anirban; Sanjeev, Sanjay deep; Agrawa, Ankit; Gupta, Aditya; Sardana, Tushar; and Chang, Zinny, "Graded Multi-Level Hysteresis Counter for Delaying Clock Stop Entry After Categorized Wakeup Events", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11982