Abstract
Clock distribution for a large integrated circuit places multiple tap points, each of which drives a local subtree of sequential sinks. Existing tools position those tap points with spatial clustering heuristics that do not account for the logical connectivity of the netlist. Logically coupled cells can therefore land in different tap domains, which may raise insertion delay, degrade clock skew, and force added hold-time buffering. To address these deficiencies, this disclosure describes a tap point estimation method that partitions sequential sinks over a hypergraph of the netlist before geometry enters the flow. A geometric dispersion check then examines each partition, and a localized physical clustering fallback divides a partition that proves physically split. The method aims to preserve logic cones under common tap points, to bound the size of the clustering problem, and to lower localized routing congestion.
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Recommended Citation
Tripathi, Shreyas; Rotival, Georges; and Bheora, Jasreet, "Tap Point Estimation for Multi-Source Clock Tree Synthesis Through Hybrid Logical and Physical Partitioning", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11980