Abstract
Redundant execution schemes for high-assurance processors have historically enforced cycle-accurate determinism across two identical cores, a constraint that can disable out-of-order execution and inflate silicon area. This publication describes a verification method in which two heterogeneous processing cores deposit execution checkpoints into a shared hardware monitor peripheral. Each checkpoint is an N-bit token (e.g., a 32-bit token in an exemplary implementation) carrying a validity bit, a checkpoint type bit, a rolling sequence number, and a payload value. The peripheral buffers each token stream in a hardware queue, compares the two queue heads, and raises a sticky, non-maskable alarm on a mismatch or a timeout. The method thereby preserves diagnostic coverage across independent clock frequencies and dissimilar pipelines.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Sinha, Rohit and Save, Prathamesh, "Asynchronous Lock-Step Execution Verification for Heterogeneous Processing Cores Through Hardware Checkpoint Comparison", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11974