Abstract
Write margins in a static random-access memory (SRAM) array shift with semiconductor process variation, and the shift grows severe at the slow-NMOS/fast-PMOS (SF) corner, where a strong pull-up network inside a storage cell resists an overwrite. A raised supply voltage widens that mismatch gap further. A write pulse modulation method addresses the problem by coupling a contention circuit to the dummy bitline of a replica timing path. The contention circuit holds an active pull-up against a dummy pull-down network, so the discharge rate of the dummy bitline follows the local ratio of PMOS drive to NMOS drive. Reset logic ends the write pulse when the dummy bitline crosses a trip point, so the pulse stretches at a skewed corner and shortens at a favorable one. The method may raise write yield across process corners and supply voltages without external voltage sensing.
Creative Commons License
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Recommended Citation
Dalal, Abhishek; Kulshrestha, Ayush; P, Ajith K.; Shamanna, Guru; and Jha, Akash, "Contention-Based Write Pulse Modulation on a Replica Timing Path for Process-Tolerant SRAM Write Operations", Technical Disclosure Commons, (September 16, 2026)
https://www.tdcommons.org/dpubs_series/11739