Abstract
Clock tree synthesis for a system on a chip can distribute a clock signal through an H-tree that feeds several tap regions. Balanced timing calls for each rectilinear clock region to carry a comparable share of a load product formed from total distance and sink capacitance. Reaching that balance over a non-binary grid has historically consumed hours of manual trial and error, in part because live queries against a physical design database respond slowly. To address these limitations disclosed is a method that caches sink coordinates and capacitance values in memory, anchors a two-by-two base grid, and injects supplemental boundary lines to reach a non-binary tile grid. Adaptive block coordinate descent then refines the shared seams over a cascading resolution schedule. The method yields gap-free, overlap-free tiles with reduced load variance in seconds.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
R, Kishore, "Automated Clock Sink Load Balancing Across Multi-Tap H-Tree Regions via Adaptive Block Coordinate Descent", Technical Disclosure Commons, (September 09, 2026)
https://www.tdcommons.org/dpubs_series/11676