Abstract
As semiconductor fabrication scales toward atomic dimensions in sub-3 nm gate-all-around (GAAFET) and complementaryFET (CFET) architectures, physical non-idealities in thin-film deposition increasingly govern chip performance, energy efficiency, and long-term reliability. Traditional computer architecture research has long abstracted the underlying silicon fabric as a set of deterministic, planar geometries characterized by nominal resistance-capacitance (RC) parasitics, treating process variation strictly through empirical statistical abstractions such as Random Dopant Fluctuations (RDF) and sub-wavelength Line Edge Roughness (LER). In reality, the physical mechanisms of Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) impart severe, deterministic spatial gradients and microscopic structural flaws that break classical microarchitectural assumptions. Gas-phase fluid dynamics and boundary layer development (δ(x) = √︁ drx/Re) inside CVD reactors induce systematic across-wafer deposition thickness gradients, while Langmuir-Hinshelwood surface kinetics create non-linear growth rates across varying partial pressures. Simultaneously, ballistic line-of-sight transport in PVD evaporation and sputtering causes severe shadow effects and cusping in high-aspectratio back-end-of-line (BEOL) trenches, producing void defects that inflate copper resistivity via Fuchs-Sondheimer surface and Mayadas-Shatzkes grain-boundary scattering by up to 3.8× and accelerate electromigration degradation by over an order of magnitude. This paper presents DepoArch, the first physics-toarchitecture co-design framework that models the architectural implications of thin-film deposition phenomena and develops microarchitectural techniques to mitigate their adverse effects. DepoArch couples Navier-Stokes fluid mechanics, Langmuir adsorption kinetics, and Knudsen ballistic transport with 3D interconnect field extraction and cycle-accurate multicore simulation. Using DepoArch, we uncover that CVD boundary layer gradients induce up to 38.4ps of deterministic clock skew across reticle-scale H-tree distribution networks, consuming 24.6% of the clock period at 4GHz and requiring costly timing guardbands. Furthermore, PVD cusping in BEOL vias elevates local current densities by 3.4×, accelerating electromigration wearout under Black’s equation and reducing mean-time-to-failure (MTTF) by 18.6×. To address these challenges, DepoArch introduces three deposition-aware architectural and physical optimizations: (1) Morphology-Aware Floorplanning (MAF), which aligns critical execution paths along isochronous deposition contours to reduce cross-core timing dispersion by 58%; (2) DepositionTolerant Clock Distribution (DT-Tree), which synthesizes asym
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Recommended Citation
Tummala, Gopi K., "DepoArch: Physics-to-Architecture Modeling and Mitigation of Thin-Film Deposition Non-Idealities in Advanced Multicore Processors", Technical Disclosure Commons, (September 08, 2026)
https://www.tdcommons.org/dpubs_series/11664