Abstract
Transistor density continues to scale with advances in semiconductor manufacturing, but limits on threshold voltage scaling have brought classical Dennard power scaling to a permanent halt. The resulting technology-imposed “utilization wall” severely restricts the fraction of silicon that can be continuously operated at maximum performance, giving rise to the dark silicon phenomenon. Because reductions in per-operation energy translate directly into increased parallel throughput under fixed thermal envelopes, specialized and heterogeneous architectures have emerged as an imperative. However, conventional parallel accelerators fail when applied to irregular integer codes characterized by tight critical paths, branch-heavy control flow, and poor memory locality. This paper presents an advanced, power-aware Conservation Core (c-core) architecture featuring an integrated on-chip Dynamic Power Management Unit (DPMU), a multi-supply voltage hierarchy, and autonomous power gating designed specifically for irregular, energy-intensive computations. Conservation cores eliminate the vast energy overheads of generalpurpose microprocessor interpretation—including instruction fetch, decode, rename, out-of-order scheduling, multiported register file access, and operand bypassing—by translating application source code directly into spatial dataflow pipelines with reverse-pipelining. To overcome the fatal static leakage penalties of advanced silicon nodes (<16nm down to 3nm GAA FinFET), our architecture introduces an on-chip closed-loop power control network. The system couples a multi-voltage programmable power supply (Integrated Voltage Regulators) and Clock Control Unit (CCU) with a distributed PMOS Power Switching Fabric. A real-time hardware Sense Vector communicates tile state (CPU, cache, and Sea of C-cores) to the DPMU. To eliminate destructive crowbar and short-circuit currents during rail collapse, specialized boundary Isolation Cells (ISO) decouple powering-down c-cores from always-on CPU and cache domains. Furthermore, an automated compilation toolchain with runtime scan-chain graph matching enables dynamic hardware patching as software evolves. Prototyped across irregular SPECint benchmarks, our power-managed conservation core architecture reduces total chip power consumption by 60% to 70%, demonstrating a robust methodology for computing under the utilization wall.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Tummala, Gopi K., "Low-Energy Conservation Cores with On-Chip Dynamic Power Management for Advanced Computations", Technical Disclosure Commons, (September 08, 2026)
https://www.tdcommons.org/dpubs_series/11655