Abstract
We disclose an FPGA architecture for a Sumcheck prover over the Mersenne-31 field using canonical-basis round polynomials of the form S(X)=A+BX. The design combines a layer-addressable Boolean-sum h-tree stored in block RAM with a banked, pipelined affine folding unit. Memory banking, ping-pong buffering, and latency-aligned control enable parallel challenge-dependent folds while respecting FPGA block-RAM constraints. The architecture is implemented and validated on a Xilinx Artix-7 FPGA and supports parameterized problem size and folding parallelism.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Mkhida, Ali, "Canonical-Basis Sumcheck Prover Architecture Using a Layer-Addressable Boolean-Sum Tree and Banked Affine Folding Pipeline", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/11648