Abstract
Achieving complete fault coverage in complex System‑on‑Chip (SoC) designs during Automated Test Pattern Generation (ATPG) can cause test pattern volume inflation, as standard Test Point Insertion (TPI) techniques distribute test points uniformly rather than targeting specific structural bottlenecks. Disclosed is a predictive test point insertion system that analyzes synthesized netlists to identify Hard‑to‑Detect (HTD) logic hierarchies through structural signature evaluation. The system parses logic cones, pinpoints structural barriers (e.g., sequential state machines, wide comparators), and concentrates test point placement within the identified HTD hierarchies. Concentrating test points into these structural bottlenecks reduces total test pattern volume while preserving fault coverage levels and maintaining physical area constraints.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Siddhapathak, Krunal; Phatak, Aditya; and Garg, Ankit, "Test Point Insertion System for Hard‑To‑Detect Hierarchies Using Netlist Structural Signature Analysis", Technical Disclosure Commons, (September 02, 2026)
https://www.tdcommons.org/dpubs_series/11581