Abstract
Hardware-level protocol proxying (HLPP) resolves latency conflicts between a host’s transaction timers and the analog wake-up of power-gated, dynamic-capacity memory in compute express link (CXL) systems. The architecture decouples the host’s error-containment domain from the memory’s physical wake-up domain using one of three distinct hardware mechanisms. One approach involves a CXL switch performing dynamic topological hot-swapping, which routes initial memory requests through an isolated, high-latency virtual path and atomically swaps to a low-latency production path after the memory awakens. In another method, a CXL memory controller performs protocol spoofing by sending synthetic shadow completion packets to the host to repeatedly reset its hardware completion timer. A third technique integrates a hardware-level error mutation gate into the host root complex that intercepts a fatal timeout signal and transmutes it into a benign cache-retry instruction. These hardware-centric solutions satisfy the host’s timers without software modification, preventing system crashes while enabling the power savings of deep power-gating and preserving error detection for genuine faults.
Keywords: hardware-level protocol proxying, dynamic-capacity memory system, topological hot-swapping, shadow completion, hardware-level error mutation, CXL fabric switch, memory controller, hardware completion-timeout timer, error containment, pooled memory
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This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Girish, Vadlamudi Venkata, "Hardware-Level Protocol Proxying for Dynamic-Capacity Memory Systems", Technical Disclosure Commons, (August 14, 2026)
https://www.tdcommons.org/dpubs_series/11359