Abstract
This publication describes systems and techniques to manage power for dynamic memory interfaces within system-on-chip architectures. In some implementations, memory paths utilize discrete operating frequencies. The described systems introduce a hardware-driven synchronization and dynamic voltage and frequency scaling (DVFS) mechanism that adjusts the active time of a memory interface based on real-time utilization. By operating the memory interface and associated requestor blocks at an elevated speed for a compressed burst period, and subsequently power-gating these components, a variable offline period is created. This synchronization effectively yields a continuous spectrum of bandwidth scaling levels. The hardware-driven approach coordinates active and inactive phases across the system to enhance memory path energy efficiency and manage thermal output while accommodating components with real-time operational constraints.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Masterson, Anthony Douglas, "Hardware-Driven Race-to-Halt (RtH) in Conjunction with Dynamic Voltage and Frequency Scaling (DVFS) for Memory Path Power Management", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10849