Abstract
A memory controller implementation for efficiently mitigating row hammering attacks in multi-channel memory systems is disclosed. The implementation addresses memory module architectures in which an alert signal pin of the memory module is shared by multiple module sub-channels. In this implementation, when the shared alert signal indicates a potential row hammering event, the memory controller stalls traffic to the memory module and transitions it to an idle state. The implementation reads status registers on the memory module to identify the affected sub-channels. Rather than broadcasting refresh management commands across all sub-channels, the memory controller unblocks the unaffected sub-channels and issues refresh management commands to only the affected sub-channels. The implementation avoids extended blackout periods for the unaffected sub-channels and promotes power efficiency by limiting the number of sub-channels that undergo a refresh operation.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Rathore, Hitender Singh; Merla, Shekar Babu; Sangaiyah, Pandithurai; and Chen, Wei-Jen, "Efficient Row Hammering Mitigation for Multi-Channel Memory Architectures", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10847