Abstract
An SRAM-based eligibility maintainer for deficit weighted round-robin scheduling stores per-queue quantum and credit in packed SRAM entries. A fixed-latency pipeline accepts multiple opcodes including CSR read, CSR write, credit decrement, and credit increment, aligned to SRAM read latency. Read-after-write correctness is provided using address-collision forwarding of in-flight write data. Per-queue eligibility is tracked in a first register vector and reload selection is tracked in a second vector indicating whether a next credit operation should reload relative to quantum. Credit updates use saturating arithmetic and threshold-aware eligibility comparisons with selectable semantics. Deterministic initialization paints SRAM with known data while defining CSR read/write behavior and suppressing datapath updates. Reload is safely gated on all active queues being ineligible, external ok_to_reload, not initializing, and no outstanding in-flight credit modifications, enabling deterministic reload without state corruption.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Anonymous, "SRAM-Based Deficit Weighted Round-Robin Eligibility Maintainer with Pipelined Read-Modify-Write Forwarding, Safe Reload, and Deterministic Initialization", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10761