Abstract
A hardware leaky-bucket rate limiter stores multiple bucket entries per SRAM row and accesses the SRAM using a unified pipeline that selects per cycle exactly one of a posted traffic request, a timer-driven scrub operation, or a CSR access. Request metadata is pipelined for SRAM read latency and updates are performed using read-modify-write. A conflict detector with forwarding supplies a most-recent-value view when a row is accessed again before a prior update is observable, avoiding lost updates. Scrub is driven by a programmable timer tick and supports per-bucket refill rates using a scrub frequency counter; an error indication asserts when a programmed iteration window is insufficient to complete a sweep. CSR accesses are given bounded latency by escalating priority after a programmable wait, disabling scrub eligibility. An initialization engine deterministically writes a pattern while controlling readiness and CSR behavior. Tx/Rx semantics may signal insufficient credits without decrementing in Rx mode.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Anonymous, "SRAM-Packed Multi-Leaky-Bucket Rate Limiter with Timer-Tick Scrubbing, Pipelined Read-Modify-Write Forwarding, and CSR Priority Escalation", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10636