Abstract
A hardware trap positioned between processing elements and a memory router and/or last-level cache intercepts tagged embedding read requests. The trap includes a dual-table structure comprising a low-frequency table that tracks access frequency for addresses without storing full embedding data and a high-frequency table that stores embedding data for addresses promoted as high-frequency. When an address exceeds a configurable promotion threshold, the trap initiates a fill request and promotes the address for local servicing. During the fill window, a configurable blocking threshold stalls additional requests for the promoted address to limit backpressure, and stalled requests are serviced upon data arrival. An aging mechanism periodically adjusts tracking state and supports eviction of stale entries. Parameters including table sizes, thresholds, and aging rates are configurable to adapt to workload characteristics exhibiting skewed access distributions.
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Recommended Citation
Anonymous, "Dual-Table Hardware Architecture for Frequency-Adaptive Memory Access Management in Accelerator Systems", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10627