Abstract

A method is disclosed for generating two or more time-aligned digital output signals — for example a differential pair such as the USB D- / D+ data lines, or more generally any paired, differential, multi-phase, polyphase, quadrature, or multi-channel synchronized output — on a microcontroller or system-on-chip that provides plural independent hardware serializer peripherals (such as two or more SPI master transmit/MOSI engines) but provides no single peripheral and no dedicated hardware capable of driving the desired multi-line signal directly.

Each output line is assigned its own serializer and preloaded with a precomputed bitstream. The serializers are started by back-to-back software trigger writes (consecutive stores to each unit's start/command register) that are preceded by CPU pipeline and memory-ordering fence instructions, which quiesce the processor so that the unavoidable inter-unit start skew becomes small, fixed, and deterministic rather than variable. That now-constant skew is then cancelled open-loop by a single fixed configured output delay applied to the later-emitting serializer (for example an SPI MOSI output delay expressed in fractions of the bit clock, dummy lead bits, or a clock-phase offset), requiring no runtime measurement or feedback. The result is that independent serializers, though triggered by separate sequential software writes, emit in alignment to within a small fraction of a bit period.

A complete reduction to practice is described in which two SPI controllers of an Espressif ESP32 synthesize a USB full-speed (12 Mbit/s) D- / D+ differential waveform, enabling software USB host signaling on a chip lacking any USB peripheral.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

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