Abstract
The technology relates to an approach for addressing parasitic capacitance in high-speed digital channels, particularly focusing on controlled-collapse chip connection flip-chip transitions. A localized inductive compensation technique involves introducing a specific series inductance through localized trace or via narrowing. The technique balances the parasitic capacitance of a solder bump to maintain a consistent characteristic impedance while preserving a continuous return path and high isolation for dense channel interfaces.
Keywords: inductive compensation, flip-chip, controlled-collapse chip connection, parasitic capacitance, characteristic impedance, high-speed digital channels.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A and , "Inductive Compensation Structure for High-Density C4 Transitions in 300G+ SerDes Applications", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10409