Abstract
As technology scales into deep submicron regimes, Multi-Processor Systems-on-Chip (MPSoCs) suffer from heightened process, environmental, and temporal variations. Traditional conservative design guardbanding severely compromises energy efficiency and performance to guarantee correctness under absolute worst-case conditions. This paper introduces a hybrid variation-tolerant multiprocessing prototype that eliminates worst-case safety margins by deploying a dual-layer adaptive architecture. At the processor core level, runtime timing speculation is realized via double-sampling Razor-like flip-flops coupled with microarchitectural clock-gating recovery. At the inter-processor and memory communication level, data corruption induced by aggressive parameters is mitigated using a parameterized Reed-Solomon (5,3) error-correcting codec operating over a FIFO-buffered interconnect channel. Prototyped and emulated on multi-FPGA systems, our design successfully mitigates single- and multi-bit dynamic timing violations, demonstrating robust dependability metrics across wide voltage-frequency configurations.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Tummala, Gopi K. and Yalamarthy, Devi, "Variability-Induced Multiprocessor: A Hybrid Let-Fail-and-Correct System Architecture", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10403