Abstract
Secondary power grid resistance verification in integrated circuit design may be hindered by the iterative nature of traditional sign‑off extraction tools. These tools may require compute time for each iteration, creating a bottleneck during the identification of resistance violations in low‑power architectures. A hierarchical machine learning framework is disclosed for the early estimation of effective resistance. In the framework, spatial tile‑based partitioning is combined with adaptive piecewise linear regression to analyze instance‑specific and spatial‑neighborhood attributes. Additionally, resistance is categorized into data‑driven zones, and zone‑specific regressors are employed to provide continuous resistance predictions. For design modifications, an incremental update scheme allows for the recalculation of only affected tiles and instances. This framework enables rapid design centering by providing feedback on resistance compliance. Through this framework, reductions in total compute time are achieved while maintaining high accuracy relative to commercial extraction tools, allowing timing risks to be addressed early in the physical design flow.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Pendyala, Prateek and Gajbhare, Sandeep, "Learning‑Based Framework for Secondary Power Grid Effective Resistance Prediction", Technical Disclosure Commons, ()
https://www.tdcommons.org/dpubs_series/10116