Abstract
Memory controllers perform periodic maintenance and training operations to preserve data integrity and link reliability. Operations (e.g., temperature sensor polling, bus training, calibration, drift compensation) occur at intervals ranging from 1 to 100 milliseconds. Implementing these timings with counters may increase area and leakage power. To address this, a disclosed method leverages periodic DRAM refresh events as a clock source for timing maintenance tasks. A down counter decrements each time a refresh signal is detected; upon reaching zero, the controller triggers the target maintenance operation and reloads the counter from a register. By utilizing the inherent periodicity of refresh cycles, this method reduces counter bit-width, effectively decreasing the memory controller’s footprint and power consumption.
Creative Commons License
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Recommended Citation
Majumder, Anirban; Sharma, Akshay; and Sangaiyah, Pandithurai, "Timing Periodic Memory Maintenance Operations Using DRAM Refresh Signals", Technical Disclosure Commons, (May 13, 2026)
https://www.tdcommons.org/dpubs_series/10114