A bottleneck in system-on-chip (SoC) development is the lengthy run times needed to identify process antenna errors between the partitions of the SoC. This disclosure describes techniques that leverage limited net extraction to rapidly identify and eliminate process antenna errors in SoCs. The hierarchies of a SoC are individually tested for process antenna effects by promoting below-top-level ports of the hierarchy and by subjecting just the promoted ports to extraction and process antenna testing. Process antenna effects at ports between partitions and within partitions are tested separately. Since the number of ports and the sizes of the partitions are relatively small compared to the SoC, port extraction and testing are rapid. By dividing the task of process antenna testing between partitions and ports, process antenna errors can be more quickly identified and eliminated.
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n/a, "Testing for Antenna-Interface Effects during System-on-Chip (SoC) Integration", Technical Disclosure Commons, (January 19, 2024)